2.Is this code is synthesizable?
always@(negedge clk or rst)
3.What is a code coverage and list the types.
4. How to swap 2 variables A and B without using 3 variable.
5. Write Verilog Code to generate 80 MHZ clock with 50% duty cycle.
Tuesday, July 15, 2008
Verilog 8
1. How to generate random number in Verilog.
2.Is this code is synthesizable?
always@(negedge clk or rst)
3.What is a code coverage and list the types.
4. How to swap 2 variables A and B without using 3 variable.
5. Write Verilog Code to generate 80 MHZ clock with 50% duty cycle.
2.Is this code is synthesizable?
always@(negedge clk or rst)
3.What is a code coverage and list the types.
4. How to swap 2 variables A and B without using 3 variable.
5. Write Verilog Code to generate 80 MHZ clock with 50% duty cycle.
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