Consider the following code,
always@(posedge clk)
begin
a=b;
b=c;
c=a;
end
What logic does the code implies.
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As a part ,for benefit to students and trainees, our team provides training and solutions .Our team first emphasizes is to, give excellent training covering the entire arena of Chip Design (front end) by providing them excellent infrastructure to become as ace Chip Designers. Our motto is to give Real Time Exposure. Support will be provided via Phone, E-mail and Chat to make your Spark ideas into Reality.
Visit:
http://www.verilogcourseteam.com/
http://www.vlsiprojects.blogspot.com/
Related Links:
http://dspprojects.blogspot.com/
http://amba-ahb.blogspot.com/
http://pci-express.blogspot.com/
http://embeddeddesignprojects.blogspot.com/
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1 comment:
It will just be a net, basically nothing is synthesized... let me know if this answer makes sense...
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