Verilog 8

1. How to generate random number in Verilog.


2.Is this code is synthesizable?
always@(negedge clk or rst)

3.What is a code coverage and list the types.

4. How to swap 2 variables A and B without using 3 variable.

5. Write Verilog Code to generate 80 MHZ clock with 50% duty cycle.

Verilog 7

Consider the following code,
always@(posedge clk)
begin
a=b;
b=c;
c=a;
end
What logic does the code implies.

Verilog 6

What is the advantage of using Gray code instead of Binary code while designing FIFO.
Write the Verilog Code for the Binary to Gray and Gray to Binary.

Verilog 5

How to test the functionality (test cases) of a FIFO.
Write the Verilog Code for the same.

Verilog 4

Consider the following code:
always@(posedge clk)
if(rst==0)
out<=1’b0;
else
out<=data_in;
a. Draw the synthesis view for the above code.
b. Modify the code for Asynchronous Reset.
c. Draw the timing diagram for synchronous and asynchronous reset.

Verilog 3

Consider the following code:
`define FALSE 0
`define TRUE 1
initial
begin
a = `FALSE;
a <= `TRUE;
if (a == `TRUE)
$display ("True");
else
$display ("False");
end
What will print out? True or False?

Verilog 2

After the first @ (posedge clk), does this do a swap?

Verilog 1

Assume b = 3 and c = 5, after the first @ (posedge clk) what is the value of a?