tag:blogger.com,1999:blog-46605726349519500622024-03-13T10:17:17.803-07:00VLSI FAQS.http://www.blogger.com/profile/12231586279374897112noreply@blogger.comBlogger19125tag:blogger.com,1999:blog-4660572634951950062.post-2375423038246781452008-07-23T06:24:00.000-07:002008-09-14T11:23:49.053-07:00Verilog Coding Guidelines- Part 5<span style="font-weight: bold;">5. FILE STRUCTURE<br /><br /></span><span style="font-weight: bold;">5.1 One file, one module<br /><br /></span>Create separate files for each modules. Name the file <module>.v. The only exceptions for this<br />file naming convention shall be the technology-dependent modules (top module or macro<br />wrapper modules). These files shall be appropriately named like design_name_fpga.v, design_name_tsmc.v, or design_name_virtex.v.<br /><br /><span style="font-weight: bold;">5.2 File header</span><br /><br />Each source file should contain a header at the top of the file in the following<br />format:<br />/////////////////////////////////////////////////////////////////<br />//////////<br />//(c) Copyright 2008 Verilog Course Team/Company Name. All rights reserved<br />//<br />// File: <filename><br />// Project: <project><br />// Purpose: <one><br />// Author: <author’s><br />//<br />// $Id: index.html,v 1.1 2008/0773/23 01:55:57 VCT $<br />//<br />// Detailed description of the module included in the file.<br />//Include relevant part of the spec<br />// Logical hierarchy tree<br />// Block diagrams<br />// Timing diagrams etc.<br />//<br />/////////////////////////////////////////////////////////////////<br /><br />The above example is for verilog. Change the comment characters appropriately for other source types. Example: "#" in Tcl, Perl and CSH. The presence of variable $Id$ in the header will capture the filename, user, version information every time the file is checked-in/committed.<br /><br /><span style="font-weight: bold;">5.3 Modification history<br /><br /></span>Each file should contain a log section at the bottom of the file in the following format:<br />///////////////////////////////////////////////////////////////////////<br />////<br />//<br />// Modification History:<br />//<br />// $Log$<br />//<br />///////////////////////////////////////////////////////////////////////<br /><br />Listing the modification history at the top of the file can be annoying as one has to scroll down to reach the code every time the file is opened for reading. The variable $Log$ will cause RCS/CVS to capture the user-comments entered during each check-in/commit as comments in footer section.<br /><br /><span style="font-weight: bold;">5.4 Include Files</span><br /><br />Keep the `define statements and Parameters for a design in a single separate file and name the file DesignName_params.v</author’s></one></project></filename></module>.http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-4660572634951950062.post-24462085743315152662008-07-23T06:20:00.000-07:002008-09-14T11:23:49.054-07:00Verilog Coding Guidelines - Part 4<span style="font-weight: bold;">4. DO’S AND DONT’S<br /><br /></span><span style="font-weight: bold;">4.1Use non-blocking assignments in sequential blocks<br /><br /></span>All registers assignments are concurrent. No combinatorial logic is allowed in sequential blocks. Always use non-blocking statements here.<br /><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiDs8J2L47vjho7kuM6orXK-2qrDkGVk6hcPZjcuvMyejVrJSr49VCR7nsk7a3Wv9-fWxlXKTMchrxFAlwyUgFXRFw_-AvGh-T-ZTUWKPsUEwakul4IfiaOUNJN7sD0ccr53Y3GrTvrqwUB/s1600-h/1.bmp"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiDs8J2L47vjho7kuM6orXK-2qrDkGVk6hcPZjcuvMyejVrJSr49VCR7nsk7a3Wv9-fWxlXKTMchrxFAlwyUgFXRFw_-AvGh-T-ZTUWKPsUEwakul4IfiaOUNJN7sD0ccr53Y3GrTvrqwUB/s400/1.bmp" alt="" id="BLOGGER_PHOTO_ID_5226199252661332466" border="0" /></a><span style="font-weight: bold;">4.2 Use blocking assignments in combinational blocks<br /><br /></span>Concurrency is not needed here. Often the combinatorial logic is implemented in multiple steps. Always use blocking statements for combinatorial blocks.<br /><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjYnTZ6P5zjiuT7ape9T2nHxG9eJE8hRF7A4yOkOWKqU7k0eYX2lXbWO2DvcPBk6yAba2eVRhRpz7-mVCEY62gXN9Eq24RiiIGVJu8LihBzAKGrQMQe_md_GIc-TBtKUvYpFP9s3o6xXXsa/s1600-h/1.bmp"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjYnTZ6P5zjiuT7ape9T2nHxG9eJE8hRF7A4yOkOWKqU7k0eYX2lXbWO2DvcPBk6yAba2eVRhRpz7-mVCEY62gXN9Eq24RiiIGVJu8LihBzAKGrQMQe_md_GIc-TBtKUvYpFP9s3o6xXXsa/s400/1.bmp" alt="" id="BLOGGER_PHOTO_ID_5226199534011510514" border="0" /></a><span style="font-weight: bold;">4.3 Ensure that there are no unused signals<br /><br /></span>Unused signals in the designs are often clear indication of incomplete or erroneous design. Check to make sure that design does not contain such signals.<br /><br /><span style="font-weight: bold;">4.3 Ensure that there are no un-driven signals<br /><br /></span>Un-driven signals in the designs are mostly clear indication of design errors. Check to make sure that design does not contain such signals..http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-4660572634951950062.post-56448395905938895602008-07-23T06:12:00.000-07:002008-09-14T11:23:49.054-07:00Verilgo Coding Guidelines -Part 3<span style="font-weight: bold;">3. COMMENT<br /><br /></span><span style="font-weight: bold;">3.1 Comment blocks vs scattered comments<br /><br /></span>Describe a group of logic at the beginning of the file (in the header) or at the top of a block or group of blocks. Avoid scattering the comment for a related logic. Typically the reader would like to go through the comment and then understand the code itself. Scattered comment can make this exercise more tedious.<br /><br /><span style="font-weight: bold;">Example:</span> <br /><br /><span style="font-weight: bold;">//File: <filename></filename></span><br /><span style="font-weight: bold;">//purpose:</span><br /><span style="font-weight: bold;">//Project:</span> <span style="font-weight: bold;"><br />//Author:<br /><br />3.2 Meaningful comments<br /><br /></span>Do not include what is obvious in the code in your comments. The comment should typically cover what is not expressed through the code itself. <span style="font-weight: bold;"><br /><br />Example:<br /><br /></span>History of a particular implementation, why a particular signal is used, any<br />algorithm being implemented etc.<br /><br /><span style="font-weight: bold;">3.3 Single line comments</span><br /><br />Use single line comments where ever possible. i.e. Use comments starting with ’//’ rather than ’/* .. */’ style. This makes it easy to cut-paste or move around the code and comments. It is also easy to follow the indentation with single line comments which makes the code more readable.<br /><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhJHBOh1m7rEuY8o8G4jxGOaSln6KQ2Z1vOi4yLdovdJhpANOLxLhlpBSk6h1b4yqSyRgxPJoVll-taoyHUEHcAssgcU4e19jynT_oud2smuNe_PUaLh3MR7obPrlZZ6zdiBjkvXqc0ULtn/s1600-h/1.bmp"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhJHBOh1m7rEuY8o8G4jxGOaSln6KQ2Z1vOi4yLdovdJhpANOLxLhlpBSk6h1b4yqSyRgxPJoVll-taoyHUEHcAssgcU4e19jynT_oud2smuNe_PUaLh3MR7obPrlZZ6zdiBjkvXqc0ULtn/s400/1.bmp" alt="" id="BLOGGER_PHOTO_ID_5226197525499159746" border="0" /></a><br /><br /><span style="font-weight: bold;"></span>.http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-4660572634951950062.post-81063121677313331652008-07-23T06:08:00.000-07:002008-09-14T11:23:49.054-07:00Verilog Coding Guidelines -Part 2<span style="font-weight: bold;">2. STYLE<br /><br /></span><span style="font-weight: bold;">2.1 Page width: 75 characters<br /><br /></span>Considering the limited page width supported in many terminals and printers, restrict the maximum line length to 75 characters. For reuse macros reduce this number to 72 to comply with RMM.<br /><br /><span style="font-weight: bold;">2.2 No tabs<br /><br /></span>Do not use tabs for indentation. Tab settings are different in different environments and hence can spoil the indentation in some setup.<br /><br /><span style="font-weight: bold;">2.3 Port ordering<br /><br /></span>Arrange the port list and declarations in a cause and effect order. Group the list/declaration on the basis of functionality rather than port direction etc. Specify the reset and clock signals at the top of the list.<br /><br /><span style="font-weight: bold;">2.4 One statement per line<br /><br /></span>Limit the number of HDL statements per line to one. Do not include multiple statements, separated by semicolon, in the same line. This will improve readability and will make it is easy to process the code using scripts and utilities.<br /><br /><span style="font-weight: bold;">2.5 One declaration per line<br /><br /></span>Limit the number of port, wire or reg declaration per line to one. Do not include multiple declarations, separated by commas, in the same line. This will make it easy to comment, add, or delete the declared objects.<br /><br /><span style="font-weight: bold;">Example:<br /><br />Wrong way:<br />input trdy_n, stop_n;<br /><br /></span><span style="font-weight: bold;">Right way:</span><br /><span style="font-weight: bold;">input trdy_n;</span><br /><span style="font-weight: bold;">input stop_n;</span>.http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-4660572634951950062.post-25711424501332335632008-07-16T04:12:00.000-07:002008-09-14T11:23:49.055-07:00Verilog Coding Guidelines -Part 1<span style="font-weight: bold;">1. Naming Conventions<br /><br />1.1 Character set</span><br /><br />Use only the characters [a-z][A-Z][0-9] $ and "_" in the identifiers used for naming module, ports, wires, regs, blocks etc.<br /><br />Do not use escaped identifiers to include special characters in identifiers. Do not use the character "_" as the first or last character of an identifier. Do not use numerals as first character.<br /><br />Do not use capital letters for identifier except Parameter and define<br /><br /><span style="font-weight: bold;">Example:conventions.v</span><br /><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEivjmPyAvkVOBRGrH0TsziRUXc9OuzStkZVBfVAb_Lu4eI0JZvRmk6CKSqu3wRE6HF9pQBjqS6QWpfKRv_167YJhk9FuV0w0hL0ODyKQfd2EGY2rEkRoZTnvaMAijuG7xPxHBiS9SzfGjMW/s1600-h/1.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEivjmPyAvkVOBRGrH0TsziRUXc9OuzStkZVBfVAb_Lu4eI0JZvRmk6CKSqu3wRE6HF9pQBjqS6QWpfKRv_167YJhk9FuV0w0hL0ODyKQfd2EGY2rEkRoZTnvaMAijuG7xPxHBiS9SzfGjMW/s400/1.JPG" alt="" id="BLOGGER_PHOTO_ID_5223568681985704114" border="0" /></a><span style="font-weight: bold;">1.2 Case sensitive</span><br /><br />Use lower case letters for all identifiers leaving the upper case letters for macros and parameters. Do not use the mixed case style. Also, ensure that all the identifiers in the design are unique even in a case insensitive environment.<br /><br /><span style="font-weight: bold;">Example: </span><br /><br /><span style="font-weight: bold;">module // keyword</span> <span style="font-weight: bold;">Module // unique identifier but not keyword<br /><br /></span> <span style="font-weight: bold;">MODULE // unique identifier but not keyword </span> <span style="font-weight: bold;">Identifier<br /><br />Name: fifoReadPointer. </span> <span style="font-weight: bold;">Use: fifo_read_pointer- instead.<br /><br />1.3 No keywords<br /><br /></span>Do not use Verilog keywords as identifiers.<br />Avoid keywords from both the HDLs as RTL code of a re-usable design may have to be made available in both languages.<span style="font-weight: bold;"><br /><br />Example:<br /><br />input –keyword<br /><br />output –keyword<br /><br />1.4 Use meaningful Names<br /><br /></span>Create identifiers by concatenating meaningful words or commonly used acronyms separated by character "_". <span style="font-weight: bold;"><br /><br />Example:<br /><br />Use en_state_transition instead of est or en_st_trn.<br /><br />1.5 Identifier length, and number of parameters<br /></span><br />Do not to use very long identifiers. This is especially true for parameters. Design unit names of parameterized modules are created by concatenating instance names, values and parameter names during design elaboration. Limit the maximum number of characters in an identifier to 25.<span style="font-weight: bold;"><br /></span><br /><span style="font-weight: bold;">1.6 Parameter/Define naming convention<br /><br /></span>Parameter and Define must be declared in Capital Letter.<br /><br /><span style="font-weight: bold;">Example:<br /><br /></span><span style="font-weight: bold;">Parameter DATA_WIDTH=3’b111 ;</span> <span style="font-weight: bold;">`define EXAMPLE<br /><br />1.7 Module names<br /></span><br />Name the top level module of the design as <design_name>_top. Module name & file name must be identical This is typically the module containing IO buffers and other technology- dependent components in addition to module <design_name>_core. Module <design_name>_core should contain only technology independent portion of the design. Name the modules created as macro wrappers <macro_name>_wrap.<br /><br /><span style="font-weight: bold;">Example:<br /><br />module test (port1,port2,…);<br />.............<br />.............<br />.............<br />endmodule<br /><br />The file should be saved as test.v<br /><br />1.8 Instance names<br /></span><br />If the module has single instance in that scope use inst_<modulename> as instance name. If there are more than one instance, then add meaningful suffixes to uniquify the names. Remember that the instance name in gate level netlist is a concatenation of RTL instance name and all the parameter ids and values in the instantiated module.<br /><br />• A module may be instantiated within another module<br />• There may be multiple instances of the same module<br />• Ports are either by order or by name<br />• Use by order unless there are lots of ports<br />• Can not mix the two syntax's in one instantiation<br />• Always use module name as instance name. <span style="font-weight: bold;"><br /><br />Example:<br /><br />memory memory_instance<br /><br />syntax for instantiation with port order:<br />module_name instance_name (signal, signal...);<br /><br />syntax for instantiation with port name:<br />module_name instance_name (.port_name(signal), .port_name (signal)… );<br /><br />1.9 Blocks names<br /><br /></span>Label all the always blocks in the RTL code with meaningful names. This will be very useful for grouping/ungrouping of the design in synthesis tool and will result in better error/info messages. It is a standard practice to append the block labels with "_comb" or "_seq" depending on whether it is combinatorial or sequential.<span style="font-weight: bold;"><br /><br />Example:<br /><br /></span></modulename></macro_name></design_name></design_name></design_name><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi9L6JD6sNy4zFpxLPY-EZH7cIT9lPqw2-tMlR_kG6yxBelN5aS61j-OhpPX_w0fV2rTTmB-Z37l7HGdWFNE9an5AR9HLK89pKqadnVKZi8jMwB6qtwo-JGu_DXRgtG5-UVrwMv4rGSZ5pF/s1600-h/1.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi9L6JD6sNy4zFpxLPY-EZH7cIT9lPqw2-tMlR_kG6yxBelN5aS61j-OhpPX_w0fV2rTTmB-Z37l7HGdWFNE9an5AR9HLK89pKqadnVKZi8jMwB6qtwo-JGu_DXRgtG5-UVrwMv4rGSZ5pF/s400/1.JPG" alt="" id="BLOGGER_PHOTO_ID_5223571058549949250" border="0" /></a><br /><span style="font-weight: bold;">1.10 Global signals<br /><br /></span>Keep same names for global signals (rst, clk etc.) in all the hierarchies of the design.<br />This should be true for any signal which are used in multiple design hierarchies. The actuals and formals in instantiation port maps should be the same IDs.<br /><br /><span style="font-weight: bold;">1.11 Clock signals</span><br /><br />Name the clock signal as clk if there is only one clock in the design. In case of multiple clocks, use _clk as suffix.<br /><br /><span style="font-weight: bold;">Example:<br /><br />pci_clk, vci_clk.<br /><br /></span>Never include the clock frequecy in clock signal name (40MHz_clk) since clock frequencies often change in the middle of the design cycle.<br /><br /><span style="font-weight: bold;">1.12 Reset signals </span><br /><br />Name the reset signal as rst if there is only one reset in the design. In case of multiple resets, use _rst as suffix.<br /><br /><span style="font-weight: bold;"> Example: </span> <span style="font-weight: bold;"><br /><br />pci_rst, vci_rst. </span><br /><br /><span style="font-weight: bold;">1.13 Active low signals </span><br /><br />All signals are lowercase alpha, numeric and underscore only. Use _n as suffix.<br /><br /><span style="font-weight: bold;">Example:<br /><br />intr_n, rst_n, irdy_n.<br /><br /></span>Avoid using characters ’#’ or ’N’ as suffixes even in documents.<br /><br /><span style="font-weight: bold;">1.14 Module Hierarchy</span><br /><br />A hierarchical path in Verilog is in form of:<br /><br />module_name.instance_name.instance_name<br /><br />top.a.b.c is the path for the hierarchy below.<br /><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhWSL1DVIbxoCBVuZQ-kkn9eF-Z2a_3uQ4PdPDLMsakzwbNM7rIw3zmMYOuGbzSSUVG_1Wi1eIrhCmUHg77bEmbrgkOIQ94eqh_Hub9I6-03DL7Ssfc_eZJkr52gHSanx9JU0BuB85vc4-f/s1600-h/1.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhWSL1DVIbxoCBVuZQ-kkn9eF-Z2a_3uQ4PdPDLMsakzwbNM7rIw3zmMYOuGbzSSUVG_1Wi1eIrhCmUHg77bEmbrgkOIQ94eqh_Hub9I6-03DL7Ssfc_eZJkr52gHSanx9JU0BuB85vc4-f/s400/1.JPG" alt="" id="BLOGGER_PHOTO_ID_5223572493280367410" border="0" /></a><span style="font-weight: bold;">1.15 Use of Macros</span><br /><br />Macros are required to be used for any non-trivial constants, and for all bit-ranges. This rule is essential both for readability and maintainability of code. Having two inter-connected modules, each of which defines a bus as '17:0' is a recipe for disaster. Busses are preferably defined with a scheme such as the following:<br /><br /><span style="font-weight: bold;">`define BUS_MSB 17<br /><br /></span><span style="font-weight: bold;">`define BUS_LSB 0 </span> <span style="font-weight: bold;"><br /><br />`define BUS_SIZE (`BUS_MSB-`BUS_LSB+1)<br /><br /></span><span style="font-weight: bold;">`define BUS_RANGE `BUS_MSB:`BUS_LSB<br /><br /></span>This will minimize the number of places that have to be changed if the bus size must be changed.<br /><br /><span style="font-weight: bold;">1.16 MEMORY DECLARTION<br /><br /></span>Memories are declared as two-dimensional arrays of registers.<br /><br /><span style="font-weight: bold;">syntax: reg [msb:lsb] identifier [first_addr:last_addr] ; </span><br /><br />where msb:lsb determine the width (word size) of the memory first_addr:last_addr determine the depth (address range) of the memory<br /><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhWJyCBvel6FqLTab44ylx_HojS8DJM3jqua6FLyBulRAnA0oVrJu3TyCPD7Wfx-vD76mZDDjXd32U21sv5LDlOfJ0v4FgVMfGKqkb62bD54aLG0nsXkhQCi8Jd-tALuOA-Rc4jzcBjjqg3/s1600-h/1.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhWJyCBvel6FqLTab44ylx_HojS8DJM3jqua6FLyBulRAnA0oVrJu3TyCPD7Wfx-vD76mZDDjXd32U21sv5LDlOfJ0v4FgVMfGKqkb62bD54aLG0nsXkhQCi8Jd-tALuOA-Rc4jzcBjjqg3/s400/1.JPG" alt="" id="BLOGGER_PHOTO_ID_5223573338352718562" border="0" /></a><span style="font-weight: bold;">1.17 Abbreviation</span><br /><br />Use consistent abbreviation as shown:<br /><br /><span style="font-weight: bold;">Signal Naming Abbreviation</span><br /><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjVUl5VWHq0LfXX07Es76ZCS3oQtH27lyMohYrcPB0dULjiJhuPZUPNERYeSKuG8i1SwodmgtkA0qMoF7rFYlAqr7VJdwSMQuIyuhyWRkd_pIToUa8buMGAJW3e3jwBktnE1POIHW0ZT6wb/s1600-h/1.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjVUl5VWHq0LfXX07Es76ZCS3oQtH27lyMohYrcPB0dULjiJhuPZUPNERYeSKuG8i1SwodmgtkA0qMoF7rFYlAqr7VJdwSMQuIyuhyWRkd_pIToUa8buMGAJW3e3jwBktnE1POIHW0ZT6wb/s400/1.JPG" alt="" id="BLOGGER_PHOTO_ID_5223573897006032146" border="0" /></a>.http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-4660572634951950062.post-90810508653820051632008-07-15T11:46:00.000-07:002008-09-14T11:17:19.184-07:00Verilog 81. How to generate random number in Verilog.<br /><br /><br />2.Is this code is synthesizable?<br /><span style="font-weight: bold;"> always@(negedge clk or rst)</span><br /><br />3.What is a code coverage and list the types.<br /><br />4. How to swap 2 variables A and B without using 3 variable.<br /><br />5. Write Verilog Code to generate 80 MHZ clock with 50% duty cycle.<br /><span style="font-size: 10pt; line-height: 115%; font-family: "Arial","sans-serif";"><a href="http://www.testbench.in/"><span style="color: windowtext; text-decoration: none;"></span></a><o:p></o:p></span>.http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-4660572634951950062.post-77181105389006363042008-07-10T03:38:00.000-07:002008-09-14T11:17:19.185-07:00Verilog 7Consider the following code,<br />always@(posedge clk)<br />begin<br />a=b;<br />b=c;<br />c=a;<br />end<br />What logic does the code implies..http://www.blogger.com/profile/12231586279374897112noreply@blogger.com1tag:blogger.com,1999:blog-4660572634951950062.post-34906016671203564442008-07-10T03:36:00.002-07:002008-09-14T11:17:19.185-07:00Synthesis 1<a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiKrc3pKWY9jkdFlAGc7RGg6vIpSZUw-631T4MvCqlQQNwfb_htRLmmrnuSAtTQ079LroZ_0guc6xvWZK8KuWt3i1I8kIup-MBsTloLlncr_UDSkUtNZoRet5MVaikuGfM1pS5CCrILrAPv/s1600-h/4.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiKrc3pKWY9jkdFlAGc7RGg6vIpSZUw-631T4MvCqlQQNwfb_htRLmmrnuSAtTQ079LroZ_0guc6xvWZK8KuWt3i1I8kIup-MBsTloLlncr_UDSkUtNZoRet5MVaikuGfM1pS5CCrILrAPv/s400/4.JPG" alt="" id="BLOGGER_PHOTO_ID_5221332846181128882" border="0" /></a><br /><br />What will be the synthesis structure?.http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-4660572634951950062.post-2955585803020643952008-07-10T03:36:00.001-07:002008-09-14T11:17:19.186-07:00Digital 4Design EX‐OR gate using 4 NAND gates.<br /><br />Design EX‐NOR gate using 4 NOR gates..http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-4660572634951950062.post-34670142192064227442008-07-10T03:35:00.000-07:002008-09-14T11:17:19.186-07:00General 1What are the parameters to be considered before starting the design work..http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-4660572634951950062.post-73253487920569541582008-07-10T03:33:00.000-07:002008-09-14T11:24:00.660-07:00Verilog 6What is the advantage of using Gray code instead of Binary code while designing FIFO.<br />Write the Verilog Code for the Binary to Gray and Gray to Binary..http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-4660572634951950062.post-31576674975760721502008-07-10T03:32:00.002-07:002008-09-14T11:24:00.660-07:00Verilog 5How to test the functionality (test cases) of a FIFO.<br />Write the Verilog Code for the same..http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-4660572634951950062.post-63748664054993979632008-07-10T03:32:00.001-07:002008-09-14T11:24:00.661-07:00Verilog 4Consider the following code:<br />always@(posedge clk)<br />if(rst==0)<br />out<=1’b0;<br />else<br />out<=data_in;<br />a. Draw the synthesis view for the above code.<br />b. Modify the code for Asynchronous Reset.<br />c. Draw the timing diagram for synchronous and asynchronous reset..http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-4660572634951950062.post-62318060796684335222008-07-10T03:31:00.003-07:002008-09-14T11:24:00.661-07:00Digital 3Draw the circuit to avoid the Set‐up and Hold‐time violation..http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-4660572634951950062.post-65222297060498359392008-07-10T03:31:00.001-07:002008-09-14T11:24:00.662-07:00Digital 2Design AND, OR gate using 2:1 mux..http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-4660572634951950062.post-7688794273205884812008-07-10T03:30:00.000-07:002008-09-14T11:24:00.662-07:00Verilog 3Consider the following code:<br />`define FALSE 0<br />`define TRUE 1<br />initial<br />begin<br />a = `FALSE;<br />a <= `TRUE;<br />if (a == `TRUE)<br />$display ("True");<br />else<br />$display ("False");<br />end<br />What will print out? True or False?.http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-4660572634951950062.post-73064480797640805422008-07-10T03:29:00.001-07:002008-09-14T11:24:00.662-07:00Verilog 2<a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj6-DqVI35Yf1Nmseilq8V1_LZ1kexlB7JZhbXuEK_VkBtrIKI9r5kKCStGLkVp_wrmciP7c-pPcLD2Q-29IXA2EPK9ceI91yZPvLJ8-qO2WtT7DOi9uKDgbKKx4e3r0C6A5v9x-m_dGPwn/s1600-h/3.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj6-DqVI35Yf1Nmseilq8V1_LZ1kexlB7JZhbXuEK_VkBtrIKI9r5kKCStGLkVp_wrmciP7c-pPcLD2Q-29IXA2EPK9ceI91yZPvLJ8-qO2WtT7DOi9uKDgbKKx4e3r0C6A5v9x-m_dGPwn/s320/3.JPG" alt="" id="BLOGGER_PHOTO_ID_5221330729069043090" border="0" /></a><br />After the first @ (posedge clk), does this do a swap?.http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-4660572634951950062.post-86550457797010502712008-07-10T03:26:00.001-07:002008-09-14T11:24:00.663-07:00Verilog 1<a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiRfG2CwyHC6d3VWgkruwMEYhv88F_WPdkaquQyYdheJO8uiAd0TpBigxf9KUsYwQGCN6uR6GwVOx98XcIWSFfODTnzJifWRJ73sc5OegyrPJMLPnRiCrxEEwJLTwSmXROJ9M8iTW-F5avf/s1600-h/3.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiRfG2CwyHC6d3VWgkruwMEYhv88F_WPdkaquQyYdheJO8uiAd0TpBigxf9KUsYwQGCN6uR6GwVOx98XcIWSFfODTnzJifWRJ73sc5OegyrPJMLPnRiCrxEEwJLTwSmXROJ9M8iTW-F5avf/s320/3.JPG" alt="" id="BLOGGER_PHOTO_ID_5221330027500408018" border="0" /></a><br />Assume b = 3 and c = 5, after the first @ (posedge clk) what is the value of a?.http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-4660572634951950062.post-5889447925719518732008-07-10T03:20:00.000-07:002008-09-14T11:24:00.663-07:00Digital 1<a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgTrS-LQ42fEm7s2nYoVlS9LPFr0hEJwxjHDGct5cqiQgdvzoEntRsDUIx_YBjaQiRJMIZmIBLBppZMhubcd4FDmzMQKvs5JjfRuf5wYDG-kq5usZXTiU_K9lAx8SJdxR88Zt9D3Kr9RjIl/s1600-h/2.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgTrS-LQ42fEm7s2nYoVlS9LPFr0hEJwxjHDGct5cqiQgdvzoEntRsDUIx_YBjaQiRJMIZmIBLBppZMhubcd4FDmzMQKvs5JjfRuf5wYDG-kq5usZXTiU_K9lAx8SJdxR88Zt9D3Kr9RjIl/s200/2.JPG" alt="" id="BLOGGER_PHOTO_ID_5221328996285413906" border="0" /></a><br /><span style="font-weight: bold;font-family:times new roman;" >Design a circuit(positive edge ) that detect the sequence when input changes</span> <span style="font-weight: bold;font-family:times new roman;" >from 0 to 1,the output should go high for only one clock pulse.</span>.http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0